Xilinx Field Programmable Gate Array, Part #: XC9572XL-7CS48I| FPGA | DEX test The ability to limit current

The ability to limit current to a known level can significantly reduce the system power requirements and bulk capacitance needed to maintain stable voltage

1x USB2 HOST/OTG

An open-drain power-good signal indicates when the output is within 93% to 107% of its nominal voltage

Data rate: 14 Gb/s

5K per 7" reel (8 mm tape)

Xilinx Field Programmable Gate Array, Part #: XC9572XL-7CS48I| FPGA | DEX test The ability to limit currentXilinx FPGA XC9572XL 7CS48IFeatures 5 ns pin to pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages 44 pin PLCC (34 user I O pins) 44 pin VQFP (34 user I O pins) 48 pin CSP (38 user I O pins) 64 pin VQFP (52 user I O pins) 100 pin TQFP (72 user I O pins) Pb free available for all packages Optimized for high performance 3. 3V systems Low power operation 5V tolerant I O pins accept